FIG. 1 is a cross-sectional view of a conventional FC package. A pattern of solder bumps 112 is formed on the side of a chip 110 that carries the integrated circuit. A complementary pattern of solder pads 122 is formed on substrate 120. Chip 110 is then flipped upside down to the orientation shown in FIG. 1, its pattern of solder bumps is aligned with the pattern of solder pads formed on substrate 120, and solder bumps 112 of chip 110 are brought into contact with solder pads 122 of substrate 120. Chip 110 and substrate 120 are then heated while in this alignment so that the solder in solder bumps 112 and solder pads 122 flows together. Upon cooling, the solder forms mechanical and electrical joints (i.e., solder joints) that connect chip 110 to substrate 120. As a result, the shape of the solder bump and pad cross-section changes from what is shown in FIG. 1 to the cross-section shown in FIG. 2. Additionally, an underfill 130 is added to the package to increase the package's structural stability.
When the solder in the solder bumps and the solder pads do not contact each other, cold joint defects result due to unsuccessful metallurgical bonding between pairs of solder bumps and solder pads. FIG. 2 is a scanning electron microphotograph of three solder joints with one cold joint in the middle and two good joints on the left and right. Since an electrical connection does not form between the solder bump and the solder pad in the cold joint, the joint fails to perform the electrical function for which it was designed.
Two factors that contribute to cold joint defects are non-coplanarity of solder bumps and poor solder bump surface quality.
First, non-uniformity of solder bump height often results in cold joints. Solder bumps are typically created in a reflow process in which the solder bumps are subjected to a temperature above their melting point so that the solder is in a liquid state, and the surface tension of the molten material pulls the material into a spherical shape. The solder bumps are allowed to cool and solidify, retaining the spherical shape. Due to process limitations, however, it is extremely difficult to ensure that all solder bumps are identical in volume. As a result, when the solder bumps are formed on the chip, the bump tips are not all at a common contact plane. This non-uniformity is further increased by the selective probing of some but not all of the solder bumps. Due to the high degree of electrical redundancy, close physical proximity, and the sheer number of solder bumps on each chip, only selected solder bumps are probed. The probing action invariably depresses the tip of the probed solder bumps, which further increases the non-coplanarity of the solder bumps.
FIG. 3 depicts three solder bumps 302, 304, and 306 of different sizes mounted on a chip 110. Solder bumps 302, 304, and 306 are aligned with solder pads 308, 310, and 312, respectively, on substrate 120. We will refer to a first solder bump as “shorter” than a second solder bump if the second solder bump extends farther from the chip surface than the first, and as “taller” than the second solder bump if the first solder bump extends farther from the chip surface than the second. Solder bump 302, as depicted, is shorter than solder bump 304, so tip 305 of solder bump 304 extends farther from chip 110 than tip 303 of solder bump 302. Since the tallest solder bumps usually determine the contact plane, the shorter solder bumps may fail to contact their solder pads. The lack of contact between the shorter solder bumps and their solder pads may prevent the formation of a physical connection between the shorter solder bumps and their solder pads, which results in cold joints.
Second, poor solder bump surface quality also results in cold joints. FIG. 4 is a photograph of the surface of a solder bump that is coated with a foreign material. This foreign material may have any of several origins. Solder bumps are sometimes coated with residual process material left behind by the reflow process. During reflow, this residual material tends to float to the solder bump tips at which the solder bumps contact the solder pads in the electronic package. Solder bumps can also develop an oxide layer when they are exposed to the atmosphere. Another source for contamination is the probe tips that are used to probe solder bumps on various chips. As the same probe is used to probe solder bump after solder bump, foreign material from one solder bump may be transferred to other solder bumps. These residual materials on the solder bumps are usually of poor electrical conductivity, and generally impede formation of physical connections between solder bumps and solder pads.
When the surface of a solder bump is coated with a material that is different from the material of the solder bump, this foreign material often prevents the material of the solder bump from contacting the material of the solder pad, which results in cold joints. Further, since the foreign material is usually of poor electrical conductivity, any connection between the coated solder bump and its solder pad via the foreign material is usually poor. The foreign material effectively functions as a barrier between the coated solder bump and the solder pad. In FIG. 3, solder bump 306 is coated with a foreign material 314. Acting as a barrier between coated solder bump 306 and solder pad 312 when the chip is packaged, foreign material 314 prevents coated solder bump 306 from contacting and forming a connection with solder pad 312, which results in a cold joint being formed. Referring again to FIG. 2, a gap between the solder bump and the solder pad in the cold joint (middle joint in FIG. 2) is clearly seen as the dark line between the solder bump and the solder pad.
In view of the foregoing discussion, it is highly desirable to provide an improved method and apparatus to prepare electronic devices that reduce cold joint defects resulting from non-coplanarity of the solder bumps and poor solder bump surface quality.